The PLA programming
The PLA programming table consists of three sections. The first section lists the product terms numerically. The second section specifies the required paths between inputs and AND gates. The third section specifies the paths between the AND and OR gates. The size of a PLA is specified by the number of inputs, the number of product terms and the number of outputs. When designing a digital system with a PLA, the internal connections of the unit are not shown. Only the PLA programming table from which the PLA can be programmed to supply the required logic is specified.
It can be classified as mask programmable of field programmable. The mask programmable PLAs are manufactured in large quantities once the PLA program table is submitted by the customer. The FPLA can be programmed by the user by means of a commercial hardware programmer unit. (Lee, 2001) Advantages Programming is simple. Disadvantages There is a limit to the combinational functions that can be implemented.
PAL is a programmable logic device with a fixed OR array and a programmable AND array.
The logic configuration of a typical PAL has a fixed number of inputs and outputs. Each input has a buffer inverted gate and each output is generated by a fixed OR gate. The output terminals are sometimes driven by 3 state buffers or inverters. The design pf PAL is facilitated by using computer-aided design techniques. The blowing of internal fuses is a hardware procedure done with the help of special electronic instruments. While designing with the PAL, the boolean functions must be simplified to fit into each section.
The product terms cannot be shared among 2 or more OR gates. The fuse map for the PAL is specified in a special programming table. For each 1 or 0 in the table, the corresponding intersection in the diagram with a symbol for an intact fuse is marked. For each dash, the diagram with blown fuses in both true and complement inputs is marked. If the AND gate is not used all the fuses are left intact. (Lee, 2001) Advantages It is easier to program. Disadvantages It is not flexible as PLAs. It was first introduced by Lattice Semiconductor.
It consists of a reprogrammable AND array, a fixed OR array, reprogrammable output logic. In addition, Electrically Erasable PROM (EEPROM, E2PROM) cells are used. It is similar to PAL except that the Output Logic MacroCells (OLMCs) form the output logic and provide more flexibility. The Output Logic MacroCell (OLMC) can be configured either for a combinational output or for a registered output. (Lee, 2001) Advantages The outputs can be made combinational or sequential. Data is retained even when power fails. Disadvantages Delay is incurred due to additional logic.
